Many semiconductor devices operate using a clock signal. This clock signal must be distributed throughout the device with as little skew as possible. One way to reduce skew is through a clock tree.
Referring now to FIG. 1, a conventional clock tree is set forth in a schematic diagram and designated by the general reference character 100. Clock tree 100 has a clock input at beginning point 140. The clock signal may be buffered by buffer circuits 110 at each T-junction 120 before being provided to circuitry at the tree ends 150. To avoid unduly cluttering the figure, buffer circuits 110 are only shown at various T-junctions 120 to illustrate a complete propagation path of a clock signal to an endpoint 150. However, it is understood that buffer circuits 110 are provided on each side of a T-junction 120. Clock tree 100 is designed such that the propagation path of a clock signal from beginning point 140 to each endpoint 150 are essentially matching. Furthermore, the delay of each buffer circuit 110 must be small to minimize the clock insertion delay from beginning point 140 to each endpoint 150.
Each buffer circuit 110 can essentially be a pair of inverters. Referring now to FIG. 2, a conventional buffer circuit is set forth in a circuit schematic diagram and designated by the general reference character 200. Conventional buffer circuit may receive a clock signal CLKIN at terminal 210 and may provide a clock signal CLKOUT at terminal 220. Buffer circuit 200 may be used as buffer circuit 110 in clock tree 100 of FIG. 1.
Buffer circuit 200 may include inverters (INV202 and INV204). Load network L202 is shown to essentially model the load of the conductive branches in the tree network of FIG. 1.
Inverter INV202 receives clock signal CLKIN at input terminal 210 and provides an output at node N212. Inverter INV204 has an input connected to node N212 and provides an output at node N214. Load L202 is connected between node N214 and output terminal 220. Input terminal 210 can be a T-junction 120 in clock tree 100 of FIG. 1 where a buffer circuit 110 and output terminal 220 can be a subsequent T-junction 120 where the next buffer circuit 110 is located.
Inverter INV202 is a complementary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET) N202 and p-channel MOSFET P202. N-channel MOSFET N202 has a gate terminal connected to input terminal 210, a source terminal connected to ground VSS, a drain terminal connected to node N212, and a body terminal connected to receive a back bias potential Vbn. P-channel MOSFET P202 has a gate terminal connected to input terminal 210, a source terminal connected to a power supply potential VDD, a drain terminal connected to node N212, and a body terminal connected to receive a back bias potential Vbp.
Inverter INV204 is a CMOS inverter including an n-channel MOSFET N204 and p-channel MOSFET P204. N-channel MOSFET N204 has a gate terminal connected to node N212, a source terminal connected to ground VSS, a drain terminal connected to node N214, and a body terminal connected to receive a back bias potential Vbn. P-channel MOSFET P204 has a gate terminal connected to node N212, a source terminal connected to a power supply potential VDD, a drain terminal connected to node N214, and a body terminal connected to receive a back bias potential Vbp.
Load L202 includes resistors (R202, R204, and R206) and capacitors (C202 and C204). Resistor R202 has a first terminal connected to node N212 and a second terminal commonly connected to a first terminal of resistor R204 and a second terminal of capacitor C202. Resistor R204 has a second terminal commonly connected to a first terminal of resistor R206 and a second terminal of capacitor C204. Resistor R206 has a second terminal connected to output terminal 220. Capacitors (C202 and C204) each have a first terminal connected to ground potential VSS.
A drawback to the conventional buffer circuit 200 is that as voltages decrease, for example, from 1 volt to 0.6 volt, the propagation delay of the clock signal can increase by a factor of 3.
Referring now to FIG. 6, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 6 illustrates the conventional buffer circuits as well as an embodiment of the present invention. In the waveform diagram of FIG. 6, signal 614 represents the clock signal CLKOUT for three series connected conventional buffer circuits 200 operating at 1.0 volts and signal 618 represents the clock signal CLKOUT for three series connected conventional buffer circuits 200 operating at 0.6 volts. As illustrated in FIG. 6, at midpoints (i.e. the trip points of a hypothetical following stage) in transitions of signal 614 and signal 618, conventional buffer circuit 200 is about 3 times slower at 0.6 volts as compared to 1.0 volts.
In view of the above, it would be desirable to provide a buffer circuit that can provide a lower signal swing voltage without substantial propagation delays. In this way, power may be reduced without the penalty of substantial propagation delays.